Verilog is basically an HDL ( Hardware Description Language ) used to model electronic systems. It is easier on a Windows machine to simulate Verilog models using software known as Xilinx ISE which is an IDE for Verilog Programming. But unfortunately, Xilinx ISE is unavailable for macOS. There are also no good IDE’s available for macOS. So we have to come from scratch by building the parts on our own. The main parts of a Verilog simulator are a place where we can write our Verilog Code and a place where we can view our result after providing the required registered values as a part of the test.
To run a Verilog code we must be having a Verilog compiler installed on our machine. The most stable available Verilog compiler is icarus-verilog and this can be easily installed using Homebrew.
Homebrew
The first and foremost important thing you must be having on your machine before moving any further is homebrew. To install Homebrew you can visit the official website or directly paste the given command in your terminal.
/usr/bin/ruby -e "$(curl -fsSL https://raw.githubusercontent.com/Homebrew/install/master/install)"icarus-verilog
The installation of icarus-verilog is now easy using Homebrew.
Install using it by typing this command in your terminal.
brew install icarus-verilogSince the compiler is ready on our machine, now we must be having an application where we can view our graphs that look something like this.
GTKWAVE
To install gtkwave you can visit this website and download it from there. You would be getting a zip file and on unzipping it and giving it required access we are ready to use GTKWAVE for our simulations.
Now let us see how we should be running Verilog Simulation on macOS step by step.
Step #1:
We can use any text/code editor to write out Verilog codes. My personal preference would be to use VS Code because there are extensions available on the VS Code marketplace that acts as IntelliSense for Verilog code.
Download VS Code from their official website and install this extension to enable Verilog Intellisense ( Note that Verilog extension is optional )
The code extension for a Verilog program is .v
Let us say we are writing a Verilog simulation for the following circuit :
Main Program
The main file would be saved as sample.v wherein we write the following code.
TestBench Program
We should also be writing a testbench program that allows us to test ut main program with some values given as the inputs, a graph is generated using which we can analyse the output properly.
The test bench program is also infact a verilog code and hence the code extension .v statys intact to the code. Let us name the testbench code to be sample_tb.v
Compile and Run
To compile and run the above code follow these steps :
(These commands have to be given in the terminal inside the directory where the main and testbench codes are present)
#1 : Compile using this command where sample_tb denotes the file name of the testbench.
iverilog -o sample_tb.vvp sample_tb.v#2 : Run the compiled code using this following command
vvp sample_tb.vvpView the timing diagram using GTKWAVE
First open the gtkwave application. To open it we have to give a command inside the terminal
open -a gtkwave
Now click on File -> New Tab or press “ ⌘ T “
Select the .vcd file which is created when we ran the testbench code.
Click at the places depicted in the image above sequentially 1 -> 2
You can see the input and output signals in the tab beneath.
Now hold the ⌘ key and select all the wires whose signals you want to analyse graphically and then click on append.
You can now view the graphs of signals that you wanted to analyse.
This is how you simulate an electrical model using Verilog on mac.
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